1. Field of the Invention
The invention relates to the field of electronic design automation, and more particularly to a system and method for efficiently performing functional verification on a multiphase circuit design.
2. Related Art
An electronic design automation (EDA) system is a computer software system used for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates (“synthesizes”) this high-level design language description into netlists of various levels of abstraction. A netlist describes the IC design and is composed of nodes (functional elements) and edges, e.g., connections between nodes. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives.
The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific (characterized) cell library that has gate-specific models for each cell (i.e., a functional element, such as an AND gate, an inverter, or a multiplexer). The models define performance parameters for the cells; e.g., parameters related to the operational behavior of the cells, such as power consumption, delay, and noise. The netlist and cell library are typically stored in computer readable media within the EDA system and are processed and verified using many well-known techniques.
FIG. 1 shows a simplified representation of an exemplary digital ASIC design flow. At a high level, the process starts with the product idea (step E100) and is realized in an EDA software design process (step E110). When the design is finalized, it can be taped-out (event E140). After tape out, the fabrication process (step E150) and packaging and assembly processes (step E160) occur resulting, ultimately, in finished chips (result E170).
The EDA software design process (step E110) is actually composed of a number of steps E112-E130, shown in linear fashion for simplicity. In an actual ASIC design process, the particular design might have to go back through steps until certain tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular ASIC.
A brief description of the components steps of the EDA software design process (step E110) will now be provided. During system design (step E112), the designers describe the functionality that they want to implement and can perform what-if planning to refine functionality, check costs, etc. Hardware-software architecture partitioning can occur at this stage. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and DesignWare® products.
During logic design and functional verification (step E114), the VHDL or Verilog code for modules in the system is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces the correct outputs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.
During synthesis and design for test (step E116), the VHDL/Verilog is translated to a netlist. The netlist can be optimized for the target technology. Additionally, the design and implementation of tests to permit checking of the finished chip occurs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® products.
During design planning (step E118), an overall floorplan for the chip is constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Jupiter and Floorplan Compiler products.
During netlist verification (step E120), the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, Formality and PrimeTime products.
During physical implementation (step E122), placement (positioning of circuit elements) and routing (connection of the same) is performed. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Astro product.
During analysis and extraction (step E124), the circuit function is verified at a transistor level, this in turn permits what-if refinement. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Star RC/XT, Raphael, and Aurora products.
During physical verification (step E126), various checking functions are performed to ensure correctness for: manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Hercules product.
During resolution enhancement (step E128), geometric manipulations of the layout are performed to improve manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the iN-Phase, Proteus, and AFGen products.
Finally, during mask data preparation (step E130), the “tape-out” data for production of masks for lithographic use to produce finished chips is performed. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the CATS® family of products.
Modern functional verification tools (such as those listed above with respect to step E114) can face difficult challenges due to the implementation techniques circuit designers use to improve circuit performance (speed). One such technique is “multiphase clocking” in which the circuit designer simulates registers through the use of several non-overlapping clocks driving latches instead of flip flops. This multiphase clocking technique can allow the timing constraints on a circuit to be relaxed, while also increasing circuit robustness. However, the multiphase clocking technique results in circuit designs (“multiphase circuit designs”) that are difficult for conventional functional verification tools to process due to the proliferation of latch elements. In an N-phase design style, a quantity “N” latches are used in place of every register, resulting in an analytical problem for the functional design tool that is N times larger than the original circuit design and exponentially more difficult to solve.
In general, conventional functional verification tools can only effectively process multiphase circuit designs that have been generated using rigid design styles. The strict limitations of such rigid design styles allow optimized circuit designs to be simplified for more efficient functional verification. For example, FIG. 2 shows a sample multiphase circuit design 200 that could be generated using a rigid two-phase design style. Circuit design 200 includes a first bank of logic B101, a first set of latches L111 coupled to receive the output of logic B101, a second bank of logic B102 coupled to receive the output of latches L111, and a second set of latches L112 coupled to receive the output of logic B102. Logic B101 operates in response to a set of inputs I0 through IN and the output of logic B102, while a set of outputs O0 through OM from latches L112 is provided as the output of circuit design 200.
The exemplary design style used to generate circuit design 200 includes the requirements that the circuit be driven by two clocks φ1 and φ2 that have opposite phases (other structural restrictions, such as the output of logic B102 only being able to feed latches L112 (and not latches L111), would also be specified by the design style). Thus, because clock φ1 feeds latches L111 and clock φ2 feeds latches L112, at any given time one set of latches will be acting like a wire, while the other set of latches will be acting like a register. In this manner, a single register can be simulated by two sets of latches, with logic B101 and B102 representing the logic originally associated with that single register. Typically, each of the banks of logic B101 and B102 will be smaller than the original logic associated with the single register, which in turn allows the logic to be made to operate faster.
For functional verification purposes, a pattern-matching operation can be performed in which a detection pattern 290 is compared with various portions of optimized circuit design 200. Detection pattern 290 is specified in the functional verification algorithm being applied to optimize circuit design 200, and is associated with an equivalent single-register implementation. Therefore, if a match is detected, the matching portion of optimized circuit design 200 (e.g., the portion encircled by the dashed line) can be transformed into a single-register implementation associated with detection pattern 290, thereby simplifying circuit design 200 for subsequent functional verification. Additional detection patterns can be used to transform different portions of optimized circuit design 200.
Unfortunately, this type of pattern-based transformation of optimized circuit design 200 is only effective when a rigid design style is used in the generation of optimized circuit design 200. Any non-conforming (i.e., syntactically different) design implementation, even if functionally equivalent (i.e., semantically identical) to detection pattern 290, will not be matched by detection pattern 290. Furthermore, conventional pattern-based transformation requires identification of all clocks (e.g., clocks φ1 and φ2), and more particularly, the relationships between those clocks, in optimized circuit design 200. Advanced timing enhancement techniques such as clock gating can make such identification non-trivial. Presently, clock identification is a manual process that is very difficult and time-consuming, and essentially requires that the circuit design being analyzed was generated using a very tightly controlled set of design specifications. Therefore, conventional functional verification techniques are not very accommodating of circuit design (and circuit designer) flexibility.
Accordingly, it is desirable to provide a system and method for performing functional verification on optimized circuit designs that does not require the use of rigid design styles and manual clock identification.